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DSP56852/d rev. 6.0 2/2004 ? motorola, inc., 2004. all rights reserved. DSP56852 preliminary technical data DSP56852 16-bit digital signal processor ? 120 mips at 120mhz 6k x 16-bit program sram 4k x 16-bit data sram 1k x 16-bit boot rom 21 external memory address lines, 16 data lines and four chip selects one (1) serial port interface (spi) or one (1) improved synchronous serial interface (issi) one (1) serial communication interface (sci) interrupt controller general purpose 16-bit quad timer jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging computer operating properly (cop)/watchdog timer 81-pin mapbga package up to 11 gpio figure 1. DSP56852 block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit pll clock generator 16-bit dsp56800e core xtal extal interrupt controller cop/ watch- dog 1 quad timer or a17, a18 2 clko muxed ( a20 ) external address bus switch external bus interface unit 6 reset irqa irqb v dd v ssio v dda v ssa external data bus switch bus control wr enable rd enable cs[2:0] muxed (gpioa) a0-16 mode d0-d12[12:0] 6 program memory 6144 x 16 sram boot rom 1024 x 16 rom data memory 4096 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr ssi or spi or gpioc sci or gpioe ipbus bridge (ipbb) 3 muxed (d13-15) 3 6 a17-18 muxed (timer pins) a19 muxed (cs3) d13-15 muxed (mode a,b,c) v ddio 6 integration module system p o r o s c decoding peripherals peripheral address decoder peripheral device selects system address decoder rw control ipab ipwdb iprdb 2 system device system bus control r/w control memory pab pab cdbw cdbr cdbw clock resets v ss 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 DSP56852 technical data preliminary part 1 overview 1.1 DSP56852 features 1.1.1 digital signal processing core efficient 16-bit dsp engine with dual harvard architecture 120 million instructions per second (mips) at 120mhz core frequency single-cycle 16 16-bit parallel multiplier-accumulator (mac) four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter parallel instruction set with unique dsp addressing modes hardware do and rep loops three (3) internal address buses and one (1) external address bus four (4) internal data buses and one (1) external data bus instruction set supports both dsp and controller functions four (4) hardware interrupt levels five (5) software interrupt levels controller-style addressing modes and instructions for compact code efficient c compiler and local variable support software subroutine and interrupt stack with depth limited only by memory jtag/enhanced once debug programming interface 1.1.2 memory harvard architecture permits as many as three simultaneous accesses to program and data memory on-chip memory includes: ? 6k 16-bit program sram ? 4k 16-bit data sram ? 1k 16-bit boot rom 21 external memory address lines, 16 data lines and four (4) programmable chip select signals 1.1.3 peripheral circuits for DSP56852 general purpose 16-bit quad timer with two external pins* one (1) serial communication interface (sci)* one (1) serial port interface (spi) or one (1) improved synchronous serial interface (issi) module* interrupt controller computer operating properly (cop)/watchdog timer jtag/enhanced on-chip emulation (eonce) for unobtrusive, real-time debugging f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
DSP56852 description DSP56852 technical data 3 preliminary 81-pin mapbga package up to 11 gpio * each peripheral i/o can be used alternately as a general purpose i/o if not needed 1.1.4 energy information fabricated in high-density cmos with 3.3v, ttl-compatible digital inputs wait and stop modes available 1.2 DSP56852 description the DSP56852 is a member of the dsp56800e core-based family of digital signal processors (dsps). on a single chip it combines the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the DSP56852 is well-suited for many applications. the DSP56852 includes many peripherals especially useful for low-end internet appliance applications and low-end client applications such as telephony; portable devices; internet audio; and point-of-sale systems such as noise suppression; id tag readers; sonic/subsonic detectors; security access devices; remote metering; and sonic alarms. the dsp56800e core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c-compilers, enabling rapid development of optimized control applications. the DSP56852 supports program execution from either internal or external memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the DSP56852 also provides two external dedicated interrupt lines, and up to 11 general purpose input/output (gpio) lines, depending on peripheral configuration. the DSP56852 dsp controller includes 6k words of program ram, 4k words of data ram and 1k of boot ram. it also supports program execution from external memory. this dsp controller also provides a full set of standard programmable peripherals that include one improved synchronous serial interface (ssi) or one serial peripheral interface (spi), one serial communications interface (sci), and one quad timer. the ssi, spi, sci i/o and three chip selects can be used as general purpose input/outputs when its primary function is not required. the ssi and spi share i/o, so, at most, one of these two peripherals can be in use at any time. 1.3 state of the art development environment processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to- use component-based software application creation with an expert knowledge system. the code warrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards will support concurrent engineering. together, pe, code warrior and evms create a complete, scalable tools solution for easy, fast, and efficient development. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 DSP56852 technical data preliminary 1.4 product documentation the four documents listed in table 1 are required for a complete description of and proper design with the DSP56852. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors/ . table 1. DSP56852 chip documentation 1.5 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800e reference manual detailed description of the dsp56800e architecture, 16-bit dsp core processor and the instruction set dsp56800erm/d DSP56852 user?s manual detailed description of memory, peripherals, and interfaces of the DSP56852 DSP56852um/d DSP56852 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56852/d DSP56852 product brief summary description and block diagram of the DSP56852 core, memory, peripherals and interfaces DSP56852pb/d DSP56852 errata details any chip issues that might be present DSP56852e/d overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for vil, vol, vih, and voh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56852 technical data 5 preliminary part 2 signal/connection descriptions 2.1 introduction the input and output signals of the DSP56852 are organized into functional groups, as shown in table 2 and as illustrated in figure 2 . in table 3 each table row describes the package pin and the signal or signals present. 1. v dd = v dd core, v ss = v ss core, v ddio = v dd io, v ssio = v ss io, v dda = v dd ana, v ssa = v ss ana 2. clkout is muxed address pin a20. 3. four address pins are multiplexed with the timer, cs3 and clkout pins. 4. cs3 is multiplexed with external address bus pin a19. 5. mode pins are multiplexed with external data pins d13-d15 like a17and a18. 6. four of these pins are multiplexed with ssi. 7. two of these pins are multiplexed with 2 bits of the external address bus a17and a18. table 2. functional group pin allocations functional group number of pins power (v dd, v ddio, or v dda ) 10 1 ground (v ss, v ssio, or v ssa ) 10 1 phase lock loop (pll) and clock 2 2 external bus signals 39 3 external chip select* 3 4 interrupt and program control 3 5 synchronous serial interface (ssi) port* 6 serial communications interface (sci) port* 2 serial peripheral interface (spi) port 0 6 quad timer module port 0 7 jtag/enhanced on-chip emulation (eonce) 6 *alternately, gpio pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 DSP56852 technical data preliminary figure 2. DSP56852 signals identified by functional group 1. specifically for pll, osc, and por. 2. alternate pin functions are shown in parentheses. DSP56852 logic power i/o power sci reset jtag/enhanced once vdd vss vddio vssio vdda vssa a0 ? 16 a17(ti/o) a18(ti/o) a19(cs3) clko(a20) gpioa0(cs0) gpioa1(cs1) gpioa2(cs2) d0-d12 d13-d15/modea-c rd wr bus control rxd(gpioe0) txd(gpioe1) gpioc0(stxd) gpioc1(srxd) sclk(gpioc2)(stck) ss (gpioc3)(stfs) miso(gpioc4)(srck) mosi(gpioc5)(srfs) irqa irqb xtal extal reset tck tdi tdo tms trst de ssi spi chip select address bus analog power 1 interrupt request oscillator data bus 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 6 6 1 1 17 1 1 1 1 1 1 1 13 3 1 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56852 technical data 7 preliminary part 3 signals and package information all digital inputs have a weak internal pull-up circuit associated with them. these pull-up circuits are enabled by default. exceptions: 1. when a pin has gpio functionality, the pull-up may be disabled under software control. 2. mode pins d13, d14 and d15 have no pull-up. 3. tck has a weak pull-down circuit always active. 4. bidirectional i/o pullups automatically disable when the output is enabled. this table is presented consistently with the signals identified by functional group figure. 1. bold entries in the type column represents the state of the pin just out of reset. 2. ouput(z) means an output in a high-z condition. table 3. DSP56852 signal and package information for the 81-pin mapbga pin no. signal name type description e1 v dd v dd logic power ? these pins provide power to the internal structures of the chip, and should all be attached to v dd. j5 v dd e9 v dd d1 v ss v ss logic power - gnd ? these pins provide grounding for the internal structures of the chip and should all be attached to v ss. j4 v ss f9 v ss c1 v ddio v ddio i/o power ? these pins provide power for all i/o and esd structures of the chip, and should all be attached to v ddio. h1 v ddio j7 v ddio g9 v ddio b9 v ddio a4 v ddio b1 v ssio v ssio i/o power - gnd ? these pins provide grounding for all i/o and esd structures of the chip and should all be attached to v ss. g1 v ssio j6 v ssio j9 v ssio c9 v ssio a5 v ssio b5 v dda v dda analog power ? these pins supply an analog power source b6 v ssa v ssa analog ground ? this pin supplies an analog ground. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 DSP56852 technical data preliminary e4 a0 output(z) address bus (a0?a16)? these pins specify a word address for external program or data memory addresses. f2 a1 f3 a2 f4 a3 f1 a4 g3 a5 g2 a6 j1 a7 h2 a8 h3 a9 j2 a10 h4 a11 g4 a12 j3 a13 f5 a14 h5 a15 e5 a16 f6 a17 tio0 output(z) input/output address bus (a17) timer i/o (0) ? can be programmed as either a timer input source or as a timer output flag. g5 a18 tio1 output(z) input/output address bus (a18) timer i/o (1) ? can be programmed as either a timer input source or as a timer output flag. h6 a19 cs3 output(z) output address bus (a19) external chip select 3 ? when enabled, a csx signal is asserted for external memory accesses that fall within a programmable address range. j8 clko a20 output output output clock (clko) ? user programmable clock out reference address bus ? a20 d2 cs0 gpioa0 output input/output chip select 0 (cs0 ) ? when enabled, a csx signal is asserted for external memory accesses that fall within a programmable address range. port a gpio (0) ? a general purpose io pin. table 3. DSP56852 signal and package information for the 81-pin mapbga pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56852 technical data 9 preliminary d3 cs1 gpioa1 output input/output chip select 1 (cs1 ) ? when enabled, a csx signal is asserted for external memory accesses that fall within a programmable address range. port a gpio (1) ? a general purpose io pin. c3 cs2 gpioa2 output input/output chip select 2 (cs2 ) ? when enabled, a csx signal is asserted for external memory accesses that fall within a programmable address range. port a gpio (2) ? a general purpose io pin. g7 d0 input /output data bus (d0 ? d12) ? specify the data for external program or data memory accesses. d0 ? d15 are tri-stated when the external bus is inactive. h7 d1 h8 d2 g8 d3 h9 d4 f8 d5 f7 d6 g6 d7 e8 d8 e7 d9 e6 d10 d8 d11 d7 d12 d9 d13 mode a input /output data bus (d13 ? d15) ? specify the data for external program or data memory accesses. d0 ? d15 are tri-stated when the external bus is inactive. mode select ? during the bootstrap process the mode a, mode b, and mode c pins select one of the eight bootstrap modes. these pins are sampled at the end of reset. note: any time por and external resets are active, the state of mode a, b and c pins get asynchronously transferred to the sim control register [14:12] ($1fff08) respectively. these bits determine the mode in which the part will boot up. note: software and cop resets do not update the sim control register. c8 d14 mode b a9 d15 mode c e2 rd output bus control ? read enable (rd ) ? is asserted during external memory read cycles. when rd is asserted low, pins d0 ? d15 become inputs and an external device is enabled onto the dsp data bus. when rd is deasserted high, the external data is latched inside the dsp. rd can be connected directly to the oe pin of a static ram or rom. table 3. DSP56852 signal and package information for the 81-pin mapbga pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 DSP56852 technical data preliminary e3 wr output bus control ? write enable (wr ) ? is asserted during external memory write cycles. when wr is asserted low, pins d0 ? d15 become outputs and the dsp puts data on the bus. when wr is deasserted high, the external data is latched inside the external device. when wr is asserted, it qualifies the a0 ? a15 pins. wr can be connected directly to the we pin of a static ram. b4 rxd gpioe0 input input/output sci receive data (rxd) ? this input receives byte- oriented serial data and transfers it to the sci receive shift register. port e gpio (0) ? a general purpose i/o pin. d4 txd gpioe1 output(z) input/output sci transmit data (txd) ? this signal transmits data from the sci transmit data register. port e gpio (1) ? a general purpose i/o pin. b2 gpioc0 stxd input /output output port c gpio (0) ? this pin is a general purpose i/o (gpio) pin when the ssi is not in use. ssi transmit data (stxd) ? this output pin transmits serial data from the ssi transmitter shift register. a2 gpioc1 srxd input /output input port c gpio (1) ? this pin is a general purpose i/o (gpio) pin when the ssi is not in use. ssi receive data (srxd) ? this input pin receives serial data and transfers the data to the ssi receive shift register. a3 sclk gpioc2 stck input /output input/output input/output spi serial clock (sclk) ? in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. port c gpio (2) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. ssi serial transfer clock (stck) ? this bidirectional pin provides the serial bit rate clock for the transmit section of the ssi. the clock signal can be continuous or gated. b3 ss gpioc3 stfs input input/output input/output spi slave select (ss ) ? in master mode, this pin is used to arbitrate multiple masters. in slave mode, this pin is used to select the slave. port c gpio (3) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. ssi serial transfer frame sync (stfs) ? this bidirectional pin is used to count the number of words in a frame while transmitting. a programmable frame rate divider and a word length divider are used for frame rate sync signal generation. table 3. DSP56852 signal and package information for the 81-pin mapbga pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56852 technical data 11 preliminary c4 miso gpioc4 srck input /output input/output input/output spi master in/slave out (miso) ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high- impedance state if the slave device is not selected. port c gpio (4) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. ssi serial receive clock (srck) ? this bidirectional pin provides the serial bit rate clock for the receive section of the ssi. the clock signal can be continuous or gated. c5 mosi gpioc5 srfs input/ output (z) input/output input/output spi master out/slave in (mosi) ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. port c gpio (5) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. ssi serial receive frame sync (srfs) ? this bidirectional pin is used to count the number of words in a frame while receiving. a programmable frame rate divider and a word length divider are used for frame rate sync signal generation. a1 irqa input external interrupt request a (irqa ) ? the irqa schmitt trigger input is a synchronized external interrupt request that indicates that an external device is requesting service. it can be programmed to be level-sensitive or negative-edge- triggered. c2 irqb input external interrupt request b (irqb ) ? the irqb schmitt trigger input is an external interrupt request that indicates that an external device is requesting service. it can be programmed to be level-sensitive or negative-edge- triggered. a6 extal input external crystal oscillator input (extal) ? this input should be connected to an external crystal. if an external clock source other than a crystal oscillator is used, extal must be tied off. a7 xtal input/ output crystal oscillator output (xtal) ? this output connects the internal crystal oscillator output to an external crystal. if an external clock source other than a crystal oscillator is used, xtal must be used as the input. table 3. DSP56852 signal and package information for the 81-pin mapbga pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12 DSP56852 technical data preliminary d5 reset input reset (reset ) ? this input is a direct hardware reset on the processor. when reset is asserted low, the dsp is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the d[15:13] pins. the internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware dsp reset is required and it is necessary not to reset the jtag/enhanced once module. in this case, assert reset , but do not assert trst . c6 tck input test clock input (tck) ? this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/enhanced once port. the pin is connected internally to a pull-down resistor. b7 tdi input test data input (tdi) ? this input pin provides a serial input data stream to the jtag/enhanced once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. a8 tdo output test data output (tdo) ? this tri-statable output pin provides a serial output data stream from the jtag/ enhanced once port. it is driven in the shift-ir and shift- dr controller states, and changes on the falling edge of tck. c7 tms input test mode select input (tms) ? this input pin is used to sequence the jtag tap controller ? s state machine. it is sampled on the rising edge of tck and has an on-chip pull- up resistor. d6 trst input test reset (trst ) ? as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment, since the enhanced once/jtag module is under the control of the debugger. in this case it is not necessary to assert trst when asserting reset . outside of a debugging environment reset should be permanently asserted by grounding the signal, thus disabling the enhanced once/jtag module on the dsp. b8 de input /output debug even (de ) ? is an open-drain, bidirectional, active low signal. as an input, it is a means of entering debug mode of operation from an external command controller. as an output, it is a means of acknowledging that the chip has entered debug mode. table 3. DSP56852 signal and package information for the 81-pin mapbga pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general characteristics DSP56852 technical data 13 preliminary part 4 specifications 4.1 general characteristics the DSP56852 is fabricated in high-density cmos with 5-volt tolerant ttl-compatible digital inputs. the term ? 5-volt tolerant ? refers to the capability of an i/o pin, built on a 3.3v compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels without being damaged. absolute maximum ratings given in table 4 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the DSP56852 dc/ac electrical specifications are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterization and device qualifications have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 4. absolute maximum ratings characteristic symbol min max unit supply voltage, core v dd 1 1. v dd must not exceed v ddio v ss ? 0.3 v ss + 2.0 v supply voltage, io supply voltage, analog v ddio 2 v ddio 2 2. v ddio and v dda must not differ by more that 0.5v v ssio ? 0.3 v ssa ? 0.3 v ssio + 4.0 v dda + 4.0 v digital input voltages analog input voltages (xtal, extal) v in v ina v ssio ? 0.3 v ssa ? 0.3 v ssio + 5.5 v dda + 0.3 v current drain per pin excluding v dd , v ss, v dda , v ssa, v ddio , v ssio i ? 10 ma junction temperature t j -40 120 c storage temperature range t stg -55 150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14 DSP56852 technical data preliminary table 5. recommended operating conditions characteristic symbol min max unit supply voltage for logic power v dd 1.62 1.98 v supply voltage for i/o power v ddio 3.0 3.6 v supply voltage for analog power v dda 3.0 3.6 v ambient operating temperature t a -40 85 c pll clock frequency 1 1. assumes clock source is direct clock to extal or crystal oscillator running 2-4mhz pll must be enabled, locked, and selected. the actual frequency depends on the source clock frequency and programming of the cgm module. f pll ? 240 mhz operating frequency 2 2. master clock is derived from one of the following four sources: f clk = f xtal when the source clock is the direct clock to exal f clk = f pll when pll is selected f clk = f osc when the source clock is the crystal oscillator and pll is not selected f clk = f extal when the source clock is the direct clock to exal and pll is not selected f op ? 120 mhz frequency of peripheral bus f ipb ? 60 mhz frequency of external clock f clk ? 240 mhz frequency of oscillator f osc 24mhz frequency of clock via xtal f xtal ? 240 mhz frequency of clock via extal f extal 24mhz table 6. thermal characteristics 1 1. see section 6.1 for more detail. characteristic 81-pin mapbga symbol value unit thermal resistance junction-to-ambient (estimated) ja 36.9 c/w i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd v dd ) + p i/o w maximum allowed p d p dmax (t j ? t a ) / ja c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dc electrical characteristics DSP56852 technical data 15 preliminary 4.2 dc electrical characteristics table 7. dc electrical characteristics operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc v dda ? 0.8 v dda v dda + 0.3 v input low voltage (xtal/extal) v ilc -0.3 ? 0.5 v input high voltage v ih 2.0 ? 5.5 v input low voltage v il -0.3 ? 0.8 v input current low (pullups disabled) i il -1 ? 1 a input current high (pullups disabled) i ih -1 ? 1 a output tri-state current low i ozl -10 ? 10 a output tri-state current high i ozh -10 ? 10 a output high voltage at i oh v oh v ddio ? 0.7 ?? v output low voltage at i ol v ol ?? 0.4 v output high current at v oh i oh 8 ? 16 ma output low current at v ol i ol 8 ? 16 ma input capacitance c in ? 8 ? pf output capacitance c out ? 12 ? pf v dd supply current (core logic, memories, peripherals) run 1 deep stop 2 light stop 3 1. running core, performing 50% nop and 50% fir. clock at 120 mhz. 2. deep stop mode - operation frequency = 4 mhz, pll set to 4 mhz, crystal oscillator. 3. light stop mode - operation frequency = 120 mhz, pll set to 240 mhz, crystal oscillator. i dd 4 4. i dd includes current for core logic, internal memories, and all internal peripheral logic circuitry. ? ? ? 55 0.02 3.4 70 2.5 8 ma ma ma v ddio supply current (i/o circuity) run 5 deep stop 2 5. running core and performing external memory access. clock at 120 mhz. i ddio ? ? 40 0 50 300 ma a v dda supply current (analog circuity) deep stop 2 i dda ? 60 120 a low voltage interrupt 6 6. when v dd drops below v ei max value, an interrupt is generated. v ei ? 2.5 2.85 v low voltage interrupt recovery hysteresis v eih ? 50 ? mv power on reset 7 7. power-on reset occurs whenever the digital supply drops below 1.8v. while power is ramping up, this signal remains active as long as the internal 2.5v is below 1.8v, no matter how long the ramp up rate is. the internally regulated voltage is typically 100mv less than v dd during ramp up until 2.5v is reached, at which time it self-regulates. por ? 1.5 2.0 v note: run (operating) i dd measured using external square wave clock source (f osc = 4mhz) into xtal. all inputs 0.2v from rail; no dc loads; outputs unloaded. all ports configured as inputs; measured with all modules enabled. pll set to 240mhz out. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16 DSP56852 technical data preliminary figure 3. maximum run i ddtotal vs. frequency (see notes 1 and 5 in table 7 ) 4.3 supply voltage sequencing and separation cautions figure 4 shows two situations to avoid in sequencing the v dd and v ddio, v dda supplies. notes: 1. v dd rising before v ddio , v dda 2. v ddio , v dda rising much faster than v dd figure 4. supply voltage sequencing and separation cautions 0 30 60 120 150 20 40 60 80 100 120 idd (ma) 90 emi mode 5 mac mode 1 3.3v 1.8v time 0 2 1 supplies stable v dd v ddio, v dda dc power supply voltage f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
supply voltage sequencing and separation cautions DSP56852 technical data 17 preliminary v dd should not be allowed to rise early (1). this is usually avoided by running the regulator for the v dd supply (1.8v) from the voltage generated by the 3.3v v ddio supply, see figure 5 . this keeps v dd from rising faster than v ddio . v dd should not rise so late that a large voltage difference is allowed between the two supplies (2). typically this situation is avoided by using external discrete diodes in series between supplies, as shown in figure 5 . the series diodes forward bias when the difference between v ddio and v dd reaches approximately 2.1, causing v dd to rise as v ddio ramps up. when the v dd regulator begins proper operation, the difference between supplies will typically be 0.8v and conduction through the diode chain reduces to essentially leakage current. during supply sequencing, the following general relationship should be adhered to: v ddio > v dd > (v ddio - 2.1v) in practice, v dda is typically connected directly to v ddio with some filtering. figure 5. example circuit to control supply sequencing 3.3v regulator 1.8v regulator supply v dd v ddio, v dda f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18 DSP56852 technical data preliminary 4.4 ac electrical characteristics timing waveforms in section 4.2 are tested with a v il maximum of 0.8v and a v ih minimum of 2.0v for all pins except xtal, which is tested using the input levels in section 4.2 . in figure 6 the levels of v ih and v il for an input signal are shown. figure 6. input signal measurement references figure 7 shows the definitions of the following signal states: active state, when a bus or signal is driven, and enters a low impedance state tri-stated, when a bus or signal is placed in a high impedance state data valid state, when a signal level has reached v ol or v oh data invalid state, when a signal level is in transition between v ol and v oh figure 7. signal states 4.5 external clock operation the DSP56852 system clock can be derived from a crystal or an external system clock signal. to generate a reference frequency using the internal oscillator, a reference crystal must be connected between the extal and xtal pins. 4.5.1 crystal oscillator for use with pll the internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in table 9 . in figure 8 a typical crystal oscillator circuit is shown. follow the crystal supplier ? s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. the crystal and associated components should be mounted as close as possible to the extal and xtal pins to minimize output distortion and start-up stabilization time. v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
external clock operation DSP56852 technical data 19 preliminary figure 8. crystal oscillator 4.5.2 high speed external clock source (> 4mhz) the recommended method of connecting an external clock is given in figure 9 . the external clock source is connected to xtal and the extal pin is held at ground (recommended), v dda , or v dda /2. the tod_sel bit in cgm must be set to 1. figure 9. connecting a high speed external clock signal using xtal 4.5.3 low speed external clock source (2-4mhz) the recommended method of connecting an external clock is given in figure 10 . the external clock source is connected to xtal and the extal pin is held at v dda /2. the tod_sel bit in cgm may be set to 0 or 1. 0 is recommended. figure 10. connecting a low speed external clock signal using xtal sample external crystal parameters: r z = 10m ? tod_sel bit in cgm may be set to 0 or 1. 0 is recommended. crystal frequency = 2 ? 4mhz (optimized for 4mhz) extal xtal r z DSP56852 xtal extal external gnd, v dda , clock (up to 240mhz) or v dda /2 DSP56852 xtal extal external clock (2-4mhz) v dda /2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20 DSP56852 technical data preliminary figure 11. external clock timing table 8. external clock operation timing requirements 4 operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit frequency of operation (external clock driver) 1 1. see figure 9 for details on using the recommended connection of an external clock driver. f osc 0 ? 240 mhz clock pulse width 4 t pw 6.25 ?? ns external clock input rise time 2, 4 2. external clock input rise time is measured from 10 to 90 percent. t rise ?? tbd ns external clock input fall time 3, 4 3. external clock input fall time is measured from 90 to 10percent. 4. parameters listed are guaranteed by design. t fall ?? tbd ns table 9. pll timing operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit external reference crystal frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 4mhz input crystal. f osc 244mhz pll output frequency f clk 40 ? 240 mhz pll stabilization time 2 2. this is the minimum time required after the pll setup is changed to ensure reliable operation. t plls ? 110ms external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
external memory interfacetiming DSP56852 technical data 21 preliminary 4.6 external memory interfacetiming the external memory interface is designed to access static memory and peripheral devices. figure 12 shows sample timing and parameters that are detailed in table 10 . the timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user controlled wait states. the equation: t = d + p * (m + w) should be used to determine the actual time of each parameter. the terms in the above equation are defined as: t parameter delay time d fixed portion of the delay, due to on-chip path delays. p the period of the system clock, which determines the execution rate of the part (i.e. when the device is operating at 120 mhz, p = 8.33 ns). m fixed portion of a clock period inherent in the design. this number is adjusted to account for possible clock duty cycle derating. w the sum of the applicable wait state controls. see the ? wait state controls ? column of table 10 for the applicable controls for each parameter. see the emi chapter of the 83x peripheral manual for details of what each wait state field controls. some of the parameters contain two sets of numbers. these parameters have two different paths and clock edges that must be considered. check both sets of numbers and use the smaller result. the appropriate entry may change if the operating frequency of the part changes. the timing of write cycles is different when wws = 0 than when wws > 0. therefore, some parameters contain two sets of numbers to account for this difference. the ? wait states configuration ? column of table 10 should be used to make the appropriate selection. figure 12. external memory interface timing t drd t rdd t ad t doh t dos t dwr t rdwr t wac t wrrd t wr t awr t wrwr t ardd t rda t rdrd t rd t arda data out data in a0-axx,cs rd wr d0-d15 note: during read-modify-write instructions and internal instructions, the address lines do not change state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
22 DSP56852 technical data preliminary table 10. external memory interface timing operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98 v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, p = 8.333ns characteristic symbol wait states configuration dm wait states controls unit address valid to wr asserted t awr wws=0 -0.75 0.50 wwss ns wws>0 -1.50 0.69 wr width asserted to wr deasserted t wr wws=0 -0.52 0.19 wws ns wws>0 -0.13 0.00 data out valid to wr asserted t dwr wws=0 -1.86 0.00 wwss ns wws=0 - 6.03 0.25 wws>0 -1.73 0.19 wws>0 -4.29 0.50 valid data out hold time after wr deasserted t doh -1.71 0.25 wwsh ns valid data out set up time to wr deasserted t dos -2.38 0.19 wws,wwss ns -4.42 0.50 valid address after wr deasserted t wac -1.44 0.25 wwsh rd deasserted to address invalid t rda - 0.51 0.00 rwsh ns address valid to rd deasserted t ardd -2.03 1.00 rwss,rws ns valid input data hold after rd deasserted t drd 0.00 n/a 1 1. n/a since device captures data before it deasserts rd ? ns rd assertion width t rd -0.97 1.00 rws ns address valid to input data valid t ad -10.13 1.00 rwss,rws ns -13.22 1.19 address valid to rd asserted t arda - 1.06 0.00 rwss ns rd asserted to input data valid t rdd -9.06 1.00 rwss,rws ns -12.65 1.19 wr deasserted to rd asserted t wrrd -0.70 0.25 wwsh,rwss ns rd deasserted to rd asserted t rdrd -0.17 2 2. if rwss = rwsh = 0, rd does not deassert during back-to-back reads and d=0.00 should be used. 0.00 rwss,rwsh ns wr deasserted to wr asserted t wrwr wws=0 -0.47 0.75 wwss, wwsh ns wws>0 -0.07 1.00 rd deasserted to wr asserted t rdwr 0.10 0.50 mdar, bmdar, rwsh, wwss ns -0.31 0.69 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reset, stop, wait, mode select, and interrupt timing DSP56852 technical data 23 preliminary 4.7 reset, stop, wait, mode select, and interrupt timing table 11. reset, stop, wait, mode select, and interrupt timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas, t = clock cycle. for f op = 120mhz operation and f ipb = 60mhz, t = 8.33ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure reset assertion to address, data and control signals high impedance t raz ? 11 ns figure 13 minimum reset assertion duration 3 3. at reset, the pll is disabled and bypassed. the part is then put into run mode and t clk assumes the period of the source clock, t xtal , t extal or t osc . t ra 30 ? ns figure 13 reset deassertion to first external address output t rda ? 120t ns figure 13 edge-sensitive interrupt request width t irw 1t + 3 ? ns figure 14 irqa , irqb assertion to external data memory access out valid, caused by first instruction execution in the interrupt service routine t idm 18t ? ns figure 15 t idm -fast 14t ? irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig 18t ? ns figure 15 t ig -fast 14t ? irqa low to first valid interrupt vector address out recovery from wait state 4 4. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the stop state. this is not the minimum required so that the irqa interrupt is accepted. t iri 22t ? ns figure 16 t iri -fast 18t ? delay from irqa assertion (exiting stop) to external data memory 5 5. the interrupt instruction fetch is visible on the pins only in mode 3. t iw 1.5t ? ns figure 17 delay from irqa assertion (exiting wait) to external data memory fast 6 normal 7 6. fast stop mode: fast stop recovery applies when external clocking is in use (direct clocking to xtal) or when fast stop mode recovery is requested (omr bit 6 is set to 1). in both cases the pll and the master clock are unaffected by stop mode entry. recovery takes one less cycle and t clk will continue same value it had before stop mode was entered. 7. normal stop mode: as a power saving feature, normal stop mode disables and bypasses the pll. stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and t clk will resume at the input clock source rate. t if 18t 22et ? ? ns ns figure 17 rsto pulse width 8 normal operation internal reset mode 8. et = external clock period, for an external crystal frequency of 8mhz, et=125 ns. t rsto 128et 8et ? ? ? ? figure 18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
24 DSP56852 technical data preliminary figure 13. asynchronous reset timing figure 14. external interrupt timing (negative-edge-sensitive) figure 15. external level-sensitive interrupt timing figure 16. interrupt from wait state timing first fetch a0 ? a20, d0 ? d15 cs , rd , wr reset first fetch t rda t ra t raz irqa irqb t irw a0 ? a20, cs , rd , wr irqa , irqb first interrupt instruction execution a) first interrupt instruction execution purpose i/o pin irqa , irqb b) general purpose i/o t ig t idm instruction fetch irqa , irqb first interrupt vector a0 ? a20, cs , rd , wr t iri f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reset, stop, wait, mode select, and interrupt timing DSP56852 technical data 25 preliminary figure 17. recovery from stop state using asynchronous interrupt timing figure 18. reset output timing not irqa interrupt vector irqa a0 ? a20, cs , rd , wr first instruction fetch t iw t if reset t rsto f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
26 DSP56852 technical data preliminary 4.8 serial peripheral interface (spi) timing 1. parameters listed are guaranteed by design. table 12. spi timing 1 operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit see figure cycle time master slave t c 25 25 ? ? ns ns figures 19 , 20 , 21 , 22 enable lead time master slave t eld ? 12.5 ? ? ns ns figure 22 enable lag time master slave t elg ? 12.5 ? ? ns ns figure 22 clock (sclk) high time master slave t ch 9 12.5 ? ? ns ns figures 19 , 20 , 21 , 22 clock (sclk) low time master slave t cl 12 12.5 ? ? ns ns figure 22 data setup time required for inputs master slave t ds 10 2 ? ? ns ns figures 19 , 20 , 21 , 22 data hold time required for inputs master slave t dh 0 2 ? ? ns ns figures 19 , 20 , 21 , 22 access time (time to data active from high-impedance state) slave t a 515 ns ns figure 22 disable time (hold time to high-impedance state) slave t d 29 ns ns figure 22 data valid for outputs master slave (after enable edge) t dv ? ? 2 14 ns ns figures 19 , 20 , 21 , 22 data invalid master slave t di 0 0 ? ? ns ns figures 19 , 20 , 21 , 22 rise time master slave t r ? ? 11.5 10.0 ns ns figures 19 , 20 , 21 , 22 fall time master slave t f ? ? 9.7 9.0 ns ns figures 19 , 20 , 21 , 22 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial peripheral interface (spi) timing DSP56852 technical data 27 preliminary figure 19. spi master timing (cpha = 0) figure 20. spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14 ? 1lsb in master msb out bits 14 ? 1 master lsb out ss (input) ss is held high on master t c t r t f t ch t cl t f t r t ch t ch t dv t dh t ds t di t di (ref) t f t r t cl sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14 ? 1lsb in master msb out bits 14 ? 1 master lsb out ss (input) ss is held high on master t r t f t c t ch t cl t ch t cl t f t ds t dh t r t di t dv (ref) t dv t f t r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
28 DSP56852 technical data preliminary figure 21. spi slave timing (cpha = 0) figure 22. spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14 ? 1 msb in bits 14 ? 1 lsb in ss (input) slave lsb out t ds t cl t cl t di t di t ch t ch t r t r t elg t dh t eld t c t f t f t d t a t dv sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14 ? 1 msb in bits 14 ? 1lsb in ss (input) slave lsb out t elg t di t ds t dh t eld t c t cl t ch t r t f t f t cl t ch t dv t a t dv t r t d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
quad timer timing DSP56852 technical data 29 preliminary 4.9 quad timer timing figure 23. timer timing table 13. timer timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas listed, t = clock cycle. for f op = 120mhz operation and fipb = 60mhz, t = 8.33ns 2. parameters listed are guaranteed by design. characteristic symbol min max unit timer input period p in 2t + 3 ? ns timer input high/low period p inhl 1t + 3 ? ns timer output period p out 2t - 3 ? ns timer output high/low period p outhl 1t - 3 ? ns timer inputs timer outputs p inhl p inhl p in p outhl p outhl p out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
30 DSP56852 technical data preliminary 4.10 synchronous serial interface (ssi) timing table 14. ssi master mode 1 switching characteristics operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. master mode is internally generated clocks and frame syncs parameter symbol min typ max units stck frequency fs 15 2 2. max clock frequency is ip_clk/4 = 60mhz / 4 = 15mhz for a 120mhz part. mhz stck period 3 3. all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync has been inverted, all the timings remain valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs in the tables and in the figures. t sckw 66.7 ns stck high time t sckh 33.4 ns stck low time t sckl 33.4 ns output clock rise/fall time 4 ns delay from stck high to stfs (bl) high - master 4 4. bl = bit length; wl = word length t tfsbhm -1.0 -0.1 ns delay from stck high to stfs (wl) high - master 4 t tfswhm -1.0 -0.1 ns delay from srck high to srfs (bl) high - master 4 t rfsbhm 0.1 1.0 ns delay from srck high to srfs (wl) high - master 4 t rfswhm 0.1 1.0 ns delay from stck high to stfs (bl) low - master 4 t tfsblm -1.0 -0.1 ns delay from stck high to stfs (wl) low - master 4 t tfswlm -1.0 -0.1 ns delay from srck high to srfs (bl) low - master 4 t rfsblm -0.1 0.1 ns delay from srck high to srfs (wl) low - master 4 t rfswlm -0.1 0.1 ns stck high to stxd enable from high impedance - master t txem 01ns stck high to stxd valid - master t txvm 01ns stck high to stxd not valid - master t txnvm -0.1 0 ns stck high to stxd high impedance - master t txhim -4 0 ns srxd setup time before srck low - master t sm 4ns srxd hold time after srck low - master t hm 4ns synchronous operation (in addition to standard internal clock parameters) srxd setup time before stck low - master t tsm 4 srxd hold time after stck low - master t thm 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
synchronous serial interface (ssi) timing DSP56852 technical data 31 preliminary figure 24. master mode timing diagram table 15. ssi slave mode 1 switching characteristics operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units stck frequency fs 15 2 mhz stck period 3 t sckw 66.7 ns stck high time t sckh 33.4 4 ns stck low time t sckl 33.4 4 ns output clock rise/fall time 4 ns delay from stck high to stfs (bl) high - slave 5 t tfsbhs -1 29 ns delay from stck high to stfs (wl) high - slave 5 t tfswhs -1 29 ns t thm t tsm t hm t sm t rfswlm t rfswhm t rfblm t rfsbhm t txhim t txnvm t txvm t txem t tfswlm t tfswhm t tfsblm t tfsbhm t sckl t sckw t sckh first bit last bit stck output stfs (bl) output stfs (wl) output stxd srck output srfs (bl) output srfs (wl) output srxd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
32 DSP56852 technical data preliminary delay from srck high to srfs (bl) high - slave 5 t rfsbhs -1 29 ns delay from srck high to srfs (wl) high - slave 5 t rfswhs -1 29 ns delay from stck high to stfs (bl) low - slave 5 t tfsbls -29 29 ns delay from stck high to stfs (wl) low - slave 5 t tfswls -29 29 ns delay from srck high to srfs (bl) low - slave 5 t rfsbls -29 29 ns delay from srck high to srfs (wl) low - slave 5 t rfswls -29 29 ns stck high to stxd enable from high impedance - slave t txes ? 15 ns stck high to stxd valid - slave t txvs 415ns stfs high to stxd enable from high impedance (first bit) - slave t ftxes 415ns stfs high to stxd valid (first bit) - slave t ftxvs 415ns stck high to stxd not valid - slave t txnvs 415ns stck high to stxd high impedance - slave t txhis 415ns srxd setup time before srck low - slave t ss 4 ? ns srxd hold time after srck low - slave t hs 4 ? ns synchronous operation (in addition to standard external clock parameters) srxd setup time before stck low - slave t tss 4 ? ? srxd hold time after stck low - slave t ths 4 ? ? 1. slave mode is externally generated clocks and frame syncs 2. max clock frequency is ip_clk/4 = 60mhz / 4 = 15mhz for a 120mhz part. 3. all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync has been inverted, all the timings remain valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length table 15. ssi slave mode 1 switching characteristics (continued) operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communication interface (sci) timing DSP56852 technical data 33 preliminary figure 25. slave mode clock timing 4.11 serial communication interface (sci) timing table 16. sci timing 4 operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max )/(32) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns t ths t tss t hs t ss t rfswls t rfswhs t rfsbls t rfsbhs t txhis t txnvs t ftxvs t txvs t ftxes t txes t tfswls t tfswhs t tfsbls t tfsbhs t sckl t sckw t sckh first bit last bit stck input stfs (bl) input stfs (wl) input stxd srck input srfs (bl) input srfs (wl) input srxd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34 DSP56852 technical data preliminary figure 26. rxd pulse width figure 27. txd pulse width figure 28. bus wakeup detection 4.12 jtag timing table 17. jtag timing 1, 3 operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for120mhz operation, t = 8.33 ns characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/4 the processor rate. 3. parameters listed are guaranteed by design. f op dc 30 mhz tck cycle time t cy 33.3 ? ns tck clock pulse width t pw 16.6 ? ns tms, tdi data setup time t ds 3 ? ns tms, tdi data hold time t dh 3 ? ns tck low to tdo data valid t dv ? 12 ns tck low to tdo tri-state t ts ? 10 ns trst assertion time t trst 35 ? ns de assertion time t de 4t ? ns rxd sci receive data pin (input) rxd pw txd sci receive data pin (input) txd pw mscan_rx can receive data pin (input) t wake-up f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
jtag timing DSP56852 technical data 35 preliminary figure 29. test clock input timing diagram figure 30. test access port timing diagram figure 31. trst timing diagram figure 32. enhanced once ? debug event tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t pw t cy input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t ts t dv t ds t dh trst (input) t trst de t de f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
36 DSP56852 technical data preliminary 4.13 gpio timing figure 33. gpio timing table 18. gpio timing operating conditions: v ss = v ssio = v ssa = 0v, v dd = 1.7-1.9v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit gpio input period p in 2t + 3 ? ns gpio input high/low period p inhl 1t + 3 ? ns gpio output period p out 2t - 3 ? ns gpio output high/low period p outhl 1t - 3 ? ns gpio inputs gpio outputs p inhl p inhl p in p outhl p outhl p out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
gpio timing DSP56852 technical data 37 preliminary part 5 DSP56852 packaging & pinout information this section contains package and pin-out information for the 81-pin mapbga configuration of the DSP56852. figure 34. bottom-view, DSP56852 81-pin mapbga package metallized mark for pin 1 identification in this area a b c d e f g h j 1 2 3 4 5 6 7 8 9 irqa gpioc1 sck v ddio v ssio td0 extal v dda tdi gpioc0 ss rxd irqb v ddio v ssio txd v ss cs0 mosi miso cs1 d14 tms tck d15 de v ssa v ddio v ssio cs2 reset rd v dd d13 d12 trst d8 v dd d11 d10 d9 a16 v ss d6 a0 wr a1 v ssio d3 v ddio d5 a17 d0 d7 a18 a12 a14 a3 a6 a5 a15 a8 a7 v ddio a11 a9 d2 a19 d1 d4 v ssio clko v ddio v ssio v dd v ss a13 a10 xtal a4 a2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
38 DSP56852 technical data preliminary table 19. DSP56852 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name e4 a0 d2 cs0 a6 extal h1 v ddio f2 a1 d3 cs1 b6 v ssa j7 v ddio f3 a2 c3 cs2 d1 v ss g9 v ddio f4 a3 g7 d0 j4 v ss b9 v ddio f1 a4 h7 d1 f9 v ss a4 v ddio g3 a5 h8 d2 b1 v ssio e2 rd g2 a6 g8 d3 g1 v ssio d5 reset j1 a7 h9 d4 j6 v ssio b4 rxd h2 a8 f8 d5 j9 v ssio a3 sck h3 a9 f7 d6 c9 v ssio a2 gpioc1 j2 a10 g6 d7 a5 v ssio b3 ss h4 a11 e8 d8 a1 irqa b2 gpioc0 g4 a12 e7 d9 c2 irqb c6 tck j3 a13 e6 d10 c4 miso b7 tdi f5 a14 d8 d11 c5 mosi a8 tdo h5 a15 d7 d12 b5 v dda c7 tms e5 a16 d9 d13e1v dd d6 trst f6 a17 c8 d14 j5 v dd d4 txd g5 a18 a9 d15e9v dd e3 wr h6 a19 b8 de c1 v ddio a7 xtal j8 clko - --- - - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
gpio timing DSP56852 technical data 39 preliminary figure 35. 81-pin mapbga mechanical information notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. case 1224b-01 issue a date 06/30/00 x 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.15 z 0.30 z z rotated 90 clockwise detail k x 0.25 y z 0.10 z 3 b 81x 4 160x dim min max millimeters a 0.95 1.3 a1 0.2 0.34 a2 0.96 ref b 0.3 0.5 d 8.00 bsc e 8.00 bsc e 0.80 bsc y detail k metalized mark for pin 1 identification in this area a b c d e f g h j 1 2 3 6 7 8 9 e 8x m m f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
40 DSP56852 technical data preliminary part 6 design considerations 6.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: t j = t a + (p d x r ja ) where: t a = ambient temperature c r ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: r ja = r jc + r ca where: r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb), or otherwise change the thermal dissipation capability of the area surrounding the device on the pcb. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. a complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junction to board thermal resistance. use the value obtained by the equation (t j ? t t )/p d where t t is the temperature of the package case determined by a thermocouple. as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical design considerations DSP56852 technical data 41 preliminary on the case of the package will estimate a junction temperature slightly hotter than actual. hence, the new thermal metric, thermal characterization parameter, or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 6.2 electrical design considerations use the following list of considerations to assure correct dsp operation: provide a low-impedance path from the board power supply to each v dd pin on the dsp, and from the board ground to each v ss (gnd) pin. the minimum bypass requirement is to place six 0.01 ? 0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the ten v dd /v ss pairs, including v dda /v ssa. ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead. use at least a four-layer printed circuit board (pcb) with two inner layers for v dd and gnd. bypass the v dd and gnd layers of the pcb with approximately 100 f, preferably with a high- grade capacitor such as a tantalum capacitor. because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and gnd circuits. all inputs must be terminated (i.e., not allowed to float) using cmos levels. take special care to minimize noise levels on the v dda and v ssa pins. when using wired-or mode on the spi or the irqx pins, the user must provide an external pull- up device. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
42 DSP56852 technical data preliminary designs that utilize the trst pin for jtag port or enhance once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer products, should tie these pins together. the internal por (power on reset) will reset the part at power on with reset asserted or pulled high but requires that trst be asserted at power on. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical design considerations DSP56852 technical data 43 preliminary part 7 ordering information table 20 lists the pertinent information needed to place an order. consult a motorola semiconductor sales office or authorized distributor to determine availability and to order parts. table 20. DSP56852 ordering information part supply voltage package type pin count frequency (mhz) order number DSP56852 1.8 ? 3.3 v mold array process ball grid array (mapbga) 81 120 DSP56852vf120 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 home page: http://motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2004 DSP56852/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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